1. Field of the Invention
The present invention relates to a display apparatus, and more particularly, to an Organic Light Emitting Diode display apparatus driven by a current and a drive method therefore.
2. Description of the Related Art
Organic Light Emitting Diode technology enables full color, full-motion flat panel displays with a level of brightness and sharpness not possible with other technologies. Unlike traditional LCD's, OLED's are self-luminous and do not require backlighting, diffusers, polarizers, or any of the other baggage that goes with liquid crystal displays. An Organic Light Emitting Diode (OLED) device is basically a piece of glass with thin-film (silicon) transistors (TFTs) with a stack of (e.g., four or five) extremely thin layers of organic materials on top of that. When a current is conducted across that stack, the organic materials glow. This luminescent phenomenon of organic compounds was first discovered in anthracene crystals (a hydrocarbon) in 1963. In 1987, Ching Tang and Steven van Slyke at Eastman Kodak (Rochester, N.Y.) formed an ultra-thin bi-layer organic light emitting diode (OLED) device with improved luminescence efficiency and stability. In late 1997 a mono-color OLED display was commercialized by Pioneer. A 5.5″ true-color OLED display was demonstrated by Sanyo-Kodak at the Society for Information Display (SID) meeting in 2000. And, in 2003 Kodak sold a digital camera that has the distinction of having been the first commercially available color OLED (organic light-emitting diode) display.
An OLED display can be driven at a lower driving current than other displays such as TFT-LCDs, PDPs, FEDs, and the like. Also, the OLED display is self-luminescent and thus exhibits high visibility. Moreover, the OLED display can have small display thickness because it does not need a backlight assembly unlike the TFT-LCD. Since the OLED display can provide a rapid response time and a wide viewing angle compared with current LCDs, it is considered as one of the next-generation flat panel displays capable of producing a high-quality moving image and a technology development for its commercialization is being actively pursued. The use of OLED displays as a display for small-sized information devices such as IMT2000, PDAs, Digital Cameras, video camera, multimedia devices and the like is rapidly increasing. OLED displays are expected to compete in the near future with the TFT-LDC in the markets of notebook computers and flat panel TVs. Because OLED production is more akin to chemical processing than semiconductor manufacturing, OLED materials could someday be applied to flexible plastic and other materials to create wall-size video panels, roll-up screens for laptops, and even wearable displays (e.g., clothes).
A data drive IC provided in an OLED display device drives a current through each pixel of an OLED panel.
FIG. 1 is a block diagram of a conventional OLED display apparatus.
Referring to FIG. 1, an OLED display device 10 receives an image data signal, a sync signal, and a clock signal from a host (not shown) and displays a color image on the OLED array.
The display device 10 includes a timing controller 100, a data drive integrated circuit (IC) 200, a voltage generator 300, a scan drive IC 400, and an OLED panel 500.
The timing controller 100 adjusts image data signals from the host to a timing required for the data drive IC 200 and the scan drive IC 400. Also, the timing controller 100 generates and outputs control signals for controlling the data drive IC 200 and the scan drive IC 400.
The voltage generator 300 provides voltages necessary for the display device 100. For example, the voltage generator 300 generates a power supply voltage (e.g., of 3.3V and 18V) for driving the data drive IC 200.
The OLED panel 500 includes data lines arranged to intersect a plurality of scan lines, and a plurality of pixels connected respectively to the scan lines and the data lines at their intersections. Each pixel includes an OLED (an organic light emitting diode).
In response to a control signal received from the timing controller 100, the scan drive IC 400 generates scan signals G0 through Gn for sequentially activating the scan lines. In this manner, all the scan lines of the OLED panel 500 are sequentially activated.
The data drive IC 200 receives image data signals DATA0 to DATAn from the timing controller 100, generates data line drive signals D0 to Dn corresponding to the received image data signals DATA0 to DATAn, and transfers the generated data line drive signals D0 to Dn through the data lines to the respective pixels.
FIG. 2 is a detailed circuit diagram of a conventional data drive IC.
Referring to FIG. 2, a data drive IC 200 includes a signal input circuit 210 and a plurality (n) of digital-to-analog converters (DACs) 220-0 to 220-n. The DACs 220-0 to 220-n correspond respectively to data lines D0 to Dn. All the DACs 220-0 to 220-n have the same circuit structure and operate in the same manner. Accordingly, only the DAC 220-0 corresponding to the first data line D0 will be illustrated and described for simplicity.
The DAC 220-0 includes level shifters 221 to 225, a step-current source circuit 230, a PMOS transistor 260, and an NMOS transistor 262. In response to each bit of an image data signal, for driving current on the data line D0, each of the level shifters 221 to 223 converts an image data signal of a power supply voltage (e.g., VDD) supplied from the signal input circuit 210 into an image data signal (e.g., DA0[0], DA0[1], . . . DA0[k-1] at a voltage level (VCCH) higher than the power supply voltage (VDD).
Base upon the driving method, the OLED matrix display can be classified as either a passive matrix or an active matrix display. Passive matrix displays adopt the method of driving the scan lines of the display in sequence, driving pixels in different rows sequentially. Active matrix displays, possess an independent pixel transistor for each pixel.
Since a passive matrix OLED display panel drives pixels by a line emission mode, it can reproduce an image of a desired brightness by instantaneously supplying a large current to the OLED pixel (e.g., by applying a high voltage (e.g., VCCH) across the OLED pixel). For example, the power supply voltage is 3.3V, and the high voltage VCCH is 18V. Therefore, the DAC 220-0 must be implemented by high-voltage devices (transistors).
The step-current source circuit 230 includes a current mirror comprising constant current source 232 and PMOS transistors 231, 241 to 24-k. The step-current source circuit 230 further includes current switching transistors 251, 252 through 25-k. The PMOS transistor 231 has a source connected to a high voltage VCCH (higher than the power supply voltage VDD), a drain and gate that are connected to the current sinking node of the constant current source 232.
Each of the PMOS transistors 241, 242 to 24-k operates as a resistor, and has its source commonly connected to the high voltage VCCH and its gate commonly connected to the gate and drain of the PMOS transistor 231. The PMOS transistors 241, 241 to 24-k are set to have different resistance values (e.g., 1R, 2R and 4R, respectively where R is a unit of resistance). The transistor 241 corresponding to the least significant bit LSB DAO[0] of the image data signal has the highest resistance value (e.g., 4R) an thus conducts the least step current (e.g., VCCH/4R), and the transistor 24-k corresponding to the most significant bit MSB DAO[k-1] of the image data signal has the lowest resistance value (e.g., 1R) an thus conducts the largest step current (e.g., VCCH/R).
By the above-structured step current source circuit 230, step (discretized) currents, corresponding to the level-shifted image data signals DO[0:k-1] from the level shifters 221 to 223, are supplied to the node N1.
The PMOS transistor 260 and the NMOS transistor 261 are serially connected between the step current source node N1 and the ground voltage. The gate of the PMOS transistor 260 is connected to an output enable signal OUTEN from the level shifter 224, and the gate of the NMOS transistor 261 is connected to a preset enable signal PSEN from the level shifter 225. A current at the common connection node between the transistors 260 and 261 is outputted as a first data line drive signal D0.
FIG. 3 is a detailed circuit diagram of the conventional level shifter 221 shown in FIG. 2. The level shifters 222 to 225 have the same circuit structure and operate in the same manner as the level shifter 221, and thus their detailed description will be omitted for simplicity.
Referring to FIG. 3, the level shifter 221 includes an inverter 271 (which may comprise two transistors) to generate a differential signal, cross coupled PMOS transistors 272 and 273, and NMOS differential input transistors 274 and 275. The PMOS transistor 272 and the NMOS transistor 274 are serially connected between the high voltage VCCH and the ground voltage, and the PMOS transistor 273 and the NMOS transistor 275 are serially connected between the high voltage VCCH and the ground voltage. The gate of the PMOS transistor 272 is connected to the gate of the NMOS transistor, and the gate of the PMOS transistor 273 is connected to the drain of the NMOS transistor 274. The voltage at a connection node between the PMOS transistor 273 and the NMOS transistor 275 is outputted as an image data signal DA0[0] that is an inputted image data signal DATA0[0] shifted into a high voltage level VCCH.
As described above, in the conventional level shifter 221, signals DATA0[0] and nDATA0[0] applied to the gates of the NMOS transistors 274 and 275 are at a power supply voltage level VDD, and the voltage applied to the gates of the PMOS transistors 272 and 273 is at a high voltage level VCCH (higher than the power supply voltage VDD). Therefore, for an exact level shift operation and an improved switching operation speed, the NMOS transistors 274 and 275 are designed to have a larger (channel) width than the PMOS transistors 272 and 273. For example, when voltage at the of one of the PMOS transistors 272 and 273 is 20V and the voltage at the gate of one of the NMOS transistors 274 and 275 is 2.2V, the NMOS transistors 274 and 275 must have more than six times the width of the PMOS transistors 272 and 273.
Referring again to FIG. 2, when a 6-bit image data signal is inputted for driving each data line D0, the binary-weighted type DAC needs 1, 2, 4, 8, 16 and 32 unit resistor transistors for six respective bits, that is, a total of 63 units or resistance in the transistors. Thus, the binary-weighted type DAC needs 63 level shifters.
By contrast, a 6-bit segment-type DAC needs a total of 10 level shifters (six for implementing resistors of 1R, 2R, 4R, 8R, 16R and 32R) plus transistors 260 and 261. As well known in the art, the 6-bit segment-type DAC least significant bit is configured to have a binary-weighted type DAC for processing LSB (least significant bit) 3 bits and a thermometer-type DAC for processing MSB (most significant bit) 3 bits. The binary-weighted type DAC for the LSB 3 bits includes three resistor transistors having ¼ times, ½ times and 1 times the size of the unit resistor transistor, respectively. The thermometer-type DAC for the MSB 3 bits includes seven resistor transistors each having ½ times the size of the unit resistor transistor. Consequently, the 6-bit segment-type DAC needs a total of ten resistor transistors classified into four types. Accordingly, ten level shifters are required.
Since a GVGA display device uses 240 data lines, a GVGA display having 6-bit segment-type DACs needs at least 2400 (240*10) level shifters. It is very burdensome to fabricate and fit 2400 level shifters 221 in the data drive IC 200 illustrated in FIG. 3.
Also, the transistor 260 illustrated in FIG. 2 must be big (wide in its channel) enough to fully transfer the full current from the node N1 as the data line drive signal D0. These big transistors cause an increase in power consumption.